1. Field of the Invention
The present invention relates to a thin-film transistor and a method of fabricating the same, and more particularly, it relates to a thin-film transistor preventing inconvenience resulting from impurity diffusion and a method of fabricating the same.
2. Description of the Background Art
With reference to FIG. 68, the structure of a conventional thin-film transistor (hereinafter referred to as TFT) 90 is described.
FIG. 68 illustrates a sectional structure of the TFT 90. Referring to FIG. 68, a first oxide film 2 is formed on a silicon substrate 1, and a pad layer 3 of polysilicon is selectively formed on the first oxide film 2. Further, a second oxide film 4 is formed to cover the first oxide film 2 and the pad layer 3.
A TFT main part 11 is formed on the second oxide film 4. The TFT main part 11 is formed by a drain 6, a channel 7, a source 8, a gate oxide film 9 which is formed on the channel 7, and a gate 10 which is formed thereon.
The drain 6, the channel 7 and the source 8 are integrally formed on a surface of the second oxide film 4 by polysilicon. The drain 6 is formed to be connected with the pad layer 3 through a contact hole 5 which is formed to reach an upper surface of the pad layer 3.
The pad layer 3, which is employed for electrically connecting the TFT 90 with another device such as a resistor or a transistor, is connected with this device (not shown).
With reference to FIGS. 69 to 73, a method of fabricating the TFT 90 is now described. The following description is made on the assumption that the TFT 90 is a P-channel TFT.
First, the first oxide film 2 is formed on the silicon substrate 1 by CVD or thermal oxidation. Then, a polysilicon film is formed on the first oxide film 2 by CVD. At this time, a phosphorus-added polysilicon film is formed by making deposition while adding phosphorus into CVD gas.
Then, the phosphorus-added polysilicon film is worked into a prescribed pattern by photolithography and etching (lithography), thereby forming the pad layer 3 as shown in FIG. 69.
Then, the second oxide film 4 is formed on the first oxide film 2 and the pad layer 3 by CVD and the contact hole 5 reaching the surface of the pad layer 3 is formed in a prescribed position by lithography, in the step shown in FIG. 70.
Then, a polysilicon film is deposited by CVD with no addition of an impurity and worked into a prescribed pattern by lithography, thereby forming a TFT layer 60 in the step shown in FIG. 71. The TFT layer 60 is adapted to define the drain 6, the channel 7 and the source 8 in a later step.
Then, an oxide film and a polysilicon film are successively deposited on the TFT layer 60 and the second oxide film 4 by CVD. At this time, a phosphorus-added polysilicon film is formed by making deposition while adding phosphorus into CVD gas.
These films are worked into prescribed patterns by lithography through a resist pattern 12 which is formed on a prescribed position, thereby forming the gate 10 and the gate oxide film 9 provided under the same as shown in FIG. 72.
Then, boron is implanted into the overall surface by ion implantation while leaving the resist pattern 12 in the step shown in FIG. 73, for converting a portion of the TFT layer 60 shown in FIG. 72 not covered with the resist pattern 12 into a P-type polysilicon film, thereby forming the P-type source 8 and the P-type drain 6 through the channel 7. Then, the resist pattern 12 is removed thereby obtaining the TFT 90 shown in FIG. 68.
The distance between the boundary between the channel 7 and the drain 6 and a peripheral edge of the contact hole 5 is referred to as a contact distance L, which is reduced when the TFT 90 is further refined and integrated.
As hereinabove described, the pad layer 3 is made of N-type polysilicon containing phosphorus as an impurity in the TFT 90 shown in FIG. 68. On the other hand, the source 8 and the drain 6 are made of P-type polysilicon containing boron as an impurity, while the drain 6 is directly connected to the pad layer 3.
Therefore, due to heat treatment in a later fabrication step such as that in a reflow step of forming a flattened film, for example, phosphorus contained in the pad layer 3 may be diffused to infiltrate into the drain 6. FIG. 74 typically illustrates the state of such phosphorus diffusion. Referring to FIG. 74, phosphorus diffused from the pad layer 3 is spread in the drain 6 along arrow.
Inconvenience resulting from such diffusion of phosphorus in the drain 6 is now described. FIG. 75 shows impurity distributions in the drain 6 and the pad layer 3.
Referring to FIG. 75, the axis of abscissas shows positions in the drain 6 and the pad layer 3, and the axis of ordinates shows the impurity concentrations. Referring to FIG. 75, symbol BP denotes the junction between the pad layer 3 and the drain 6, i.e., the surface position of the pad layer 3. The left and right sides of the junction BP show the states in the drain 6 and the pad layer 3 respectively.
Referring to FIG. 75, the distribution state of phosphorus before heat treatment is shown by a thick line as a distribution chart Q. On the hand, the distribution state of phosphorus after the heat treatment is shown as a distribution chart R. Further, the distribution state of boron after the heat treatment is shown as a distribution chart S. As understood from the distribution chart Q, phosphorus, which is present only in the pad layer 3 before the heat treatment, is diffused in the drain 6 due to the heat treatment. When the concentration of diffused phosphorus is higher than that of boron, phosphorus cancels the action of boron in the drain 6, i.e., compensates boron, to convert the drain 6 to an N type in a constant area from the junction BP.
No problem arises if the distance (hereinafter referred to as a interboundary distance) between the junction BP and the boundary between the channel 7 and the drain 6 is sufficiently longer than the length of the constant area which is converted to an N type. However, the contact distance L tends to be shortened following refinement and integration of the TFT 90 as described above, and hence the interboundary distance is also reduced.
When the interboundary distance is below the length of the aforementioned constant area, i.e., if the concentration of diffused phosphorus is higher than that of boron and the phosphorus diffusion area exceeds the boron diffusion area, the overall drain 6 of the TFT 90 is disadvantageously converted to an N type.
In this case, the TFT 90 forms not a PNP transistor but a PNN diode. FIG. 76 shows the operating characteristics of the TFT 90. Referring to FIG. 76, characteristic curves T and U show the operation characteristics of a normal TFT 90 and a TFT forming a diode due to conversion of the drain 6 to an N type. Referring to FIG. 76, the right and left sides of the origin on the axis of abscissas show negative and positive gate voltages, while the upper side of the origin on the axis of ordinates shows negative drain currents.
As shown in FIG. 76, a drain current hardly flows and a leakage current is small while the gate is supplied with a positive voltage if the TFT 90 is normal. If the TFT 90 forms a diode, however, the drain current cannot be cut off and an abnormal leakage current flows even if the gate is supplied with a positive voltage.
While this problem can be solved by preparing the pad layer 3 from P-type polysilicon, this pad layer 3 may have to be of an N type depending on the other device connected with the TFT 90. In an SRAM or the like, for example, this pad layer 3 may be connected to an N-type diffusion layer on the silicon substrate 1, and an unintended parasitic P-N junction (i.e., a diode) is formed across the pad layer 3 (P-type polysilicon) and the N-type diffusion layer (single-crystalline silicon) if the pad layer 3 is of a P type.
Rectification characteristics of this diode are relatively remarkable, and electric resistance in reverse bias extremely damages the circuit characteristics. On the other hand, rectification characteristics of the parasitic P-N junction formed on the junction between polysilicon layers such as the drain 6 and the pad layer 3 of the TFT 90, i.e., a diode, are dull and electric resistance in reverse bias is small.
The characteristics of a diode formed between polysilicon layers become dull due to a number of crystal defects which are present in polysilicon. Namely, the crystal defects form levels in a band gap and electrons and holes contained in the crystal defects flow in positive and negative directions in reverse bias of the parasitic P-N junction, to generate a number of currents (generation currents).
When the pad layer 3 is made of P-type polysilicon, the P-type impurity contained in the pad layer 3 infiltrates into the N-type diffusion layer on the silicon substrate 1, to reach the silicon substrate 1 and cause a short-circuit state, as the case may be.